modelsim makefile

Ref: https://github.com/potentialventures/cocotb/blob/master/makefiles/simulators/Makefile.modelsim

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VPI_LIB := vpi

# Modelsim is 32-bit only
ARCH:=i686

ifdef VERILOG_INCLUDE_DIRS
VLOG_ARGS += +incdir+$(VERILOG_INCLUDE_DIRS)
endif

ifeq ($(GUI),1)
SIM_CMD = vsim -gui
VSIM_ARGS += -onfinish stop
else
SIM_CMD = vsim -c
VSIM_ARGS += -onfinish exit
endif

ifeq ($(GPI_IMPL),vhpi)
VSIM_ARGS += -foreign \"cocotb_init libfli.so\" -trace_foreign 3
else
VSIM_ARGS += -pli libvpi.$(LIB_EXT)
endif

$(SIM_BUILD)/runsim.do : $(VHDL_SOURCES) $(VERILOG_SOURCES) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
echo "vlib work" > $@
ifneq ($(VERILOG_SOURCES),)
echo "vlog -timescale 1ns/100ps -mfcu +acc=rmb -sv $(VLOG_ARGS) $(VERILOG_SOURCES)" >> $@
else
echo "vcom $(VHDL_ARGS) $(VHDL_SOURCES)" >> $@
endif
echo "vsim $(VSIM_ARGS) $(TOPLEVEL)" >> $@
ifneq ($(GUI),1)
echo "run -all" >> $@
echo "quit" >> $@
endif


ifeq ($(OS),MINGW32_NT-6.1)

ifeq ($(MODELSIM_PATH),)
$(error "Need to set MODELSIM_PATH")
endif

EXTRA_LIBS := -lmtipli
EXTRA_LIBDIRS := -L$(MODELSIM_PATH)/win32aloem
OLD_PATH := $(shell echo "$(PATH)" | sed 's/(/\\(/g' | sed 's/)/\\)/g' | sed 's/ /\\ /g')
LIB_LOAD := PATH=$(OLD_PATH):$(LIB_DIR)

else
LIB_LOAD := LD_LIBRARY_PATH=$(LIB_DIR):$(LD_LIBRARY_PATH)
endif

results.xml: $(SIM_BUILD)/runsim.do $(COCOTB_LIBS) $(COCOTB_VPI_LIB)
cd $(SIM_BUILD) && $(LIB_LOAD) MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) \
PYTHONPATH=$(LIB_DIR):$(SIM_ROOT):$(PWD):$(PYTHONPATH) \
$(SIM_CMD) -do runsim.do 2>&1 | tee sim.log

clean::
-rm -rf $(SIM_BUILD)

modelsim xilinx library

 第一次使用modelsim SE的时候，要编译库后才能够使用，一般网上有用命令行方式编译，但是xilinx为我们提供了一个GUI界面，呵呵，相当方便。

        在终端输入compxlibgui，这个就出现了编译库的界面，相当简单，如果要全部编译，一直点next即可。哈哈（但是前提要安装了xilinx ISE）。

编译后的库文件在H:/Xilinx13/ISE_DS/ISE/verilog/mti_se/6.5/nt/中，其中xilinxcorelib_ver是IP核行为级验证模型。

--------------------仿真Sram

利用Modelsim脚本编译的时候，需要加入glbl.v

#vlog D:/SVN_code/Xilinx/RSA2048/ipcore_dir/BLK_MEM_GEN_V6_1.v
vlog D:/SVN_code/Xilinx/RSA2048/ipcore_dir/sram1.v

vlog H:/Xilinx13/ISE_DS/ISE/verilog/src/glbl.v

vsim -L H:/Xilinx13/ISE_DS/ISE/verilog/mti_se/6.5/nt/xilinxcorelib_ver -novopt work.testbench glbl

当然，假如只用SRAM一个IP的话，可以只编译BLK_MEM_GEN_V6_1.v即可。

但是注意`timescale的定义，在BLK_MEM_GEN_V6_1.v中，定义的是绝对延时，比如输出数据的latency会有FLOP_DELAY个ps，所以在设计文件中的时钟频率不能太高，否则会出现多周期的延时，一般设置为`timescale 1ns/1ps